In the manufacture of semiconductor devices, silicides, materials formed by the reaction of a refractory metal or a near-noble metal with silicon, are used in a variety of applications. For example, these materials may be used as a contact via fill material, or as a device structure such as a floating gate or a local interconnect.
It is normally necessary to make contact to device regions underlying a dielectric on the surface of the silicon substrate. This is accomplished by first forming an opening or via (contact via) in the dielectric over the region to be contacted, and next filling the contact via with a conductive material.
After the contact vias have been filled with a conductive material, it is then necessary to electrically connect certain device regions with others, as well as to provide for electrical connection to external leads. These requirements are met by forming a wiring layer on the surface of the substrate. The wiring layer is formed by depositing a conductive layer that is in direct contact with the contact fills previously formed. The conductive layer is then masked and etched to leave continuous lines of the conductive material necessary to make the appropriate connections to the device regions of the substrate underlying the contact fill. These lines are known as interconnects.
Several conductive materials can be used as a contact via fill. In larger geometry devices, aluminum (Al) is deposited on the entire substrate, including over the vias. The areas over the vias and interconnects are then masked with photoresist and the aluminum is etched from the remaining areas, leaving the vias filled with aluminum as well as forming interconnects on the surface of the dielectric layer.
In smaller geometry devices, those one micron or less, aluminum has proven to be inadequate as a fill due to problems such as poor step coverage and poor contact integrity. For these devices, silicides of refractory or nearnoble metals, such as titanium or cobalt, are used as the initial fill material filling the lower portion of the via in contact with the substrate. The metal is first deposited followed by an anneal to form the silicide on the substrate in the regions exposed by the via. The non-silicidized metal remaining on the dielectric surface is then selectively etched. Because the silicide is formed only on those regions where there is silicon exposed, that is, the active device regions, and the remaining metal can be selectively etched without a masking step, the structure formed by this process is self aligned. This process is an example of self aligned silicide technology ("salicide technology").
After the silicide formation in the lower portion of the via is completed, it is then necessary to fill the unfilled upper portion of the via with aluminum or another conductive material and to form interconnects as described above. However, if aluminum is deposited directly on silicide, the aluminum frequently will diffuse through the silicide into the underlying active device region of the substrate, causing device failure. This phenomenon is known as spiking. To prevent spiking it is necessary in the prior art techniques described above to form a diffusion barrier prior to aluminum deposition. This is accomplished by first depositing an additional dielectric layer. That deposition is followed by masking and etching steps to remove the dielectric from the via regions. A thin layer of titanium, titanium nitride or titanium tungsten is formed to act as a diffusion barrier. The aluminum is then deposited, masked and etched from unmasked portions along with the aluminum. See for example U.S. Pat. No. 4,566,026 where titanium tungsten nitride/titanium nitride bilayer is used as a diffusion barrier against spiking.
Another alternative is to form the silicide as described above, and next grow a selective tungsten layer to fill the via. However, selective tungsten deposition generally leads to degradation of the junction integrity and unacceptably high specific contact resistivity.
Alternatively, in the prior art, after the self aligned silicide formation described above, a doped selective silicon layer is grown on top of the silicide layer to completely fill the via. Selective silicon has improved junction integrity, that is, good diode I-V characteristics such as low reverse bias leakage current and a good ideality factor. A problem with this method is that during drive-in and subsequent high temperature steps, excessive dopant from the selective silicon layer may diffuse into the active regions and change the device performance characteristics. Additionally, in CMOS devices, to prevent the formation of unintended p-n junctions it is necessary to first grow p-type selective silicon over the p-type regions keeping the n-type regions masked, and then grow n-type selective silicon over the n-type regions using an n-type dopant such as arsenic, phosphorous or antimony, keeping the p-type regions masked during this step.
In addition to via fill applications, the salicide technology described above can be used for forming other device regions. For example, the technology can be used to form a silicide on top of polysilicon to be used as a floating gate. Additionally, local interconnects can be formed using this technology after deposition, masking and etch of a polysilicon layer.
In the prior art, titanium silicide and cobalt silicide are the two most commonly used silicides for salicide technology. However, the formation of cobalt silicide is impeded by the presence of a native oxide on the substrate surface. This can be overcome by performing a high temperature heating on the substrate immediately before deposition, and then depositing the cobalt under ultra high vacuum. Such ultra high vacuum systems however are generally for use in research, but do not have the throughput capabilities needed for volume production.
What is needed is a manufacturable method of forming a high quality silicide compatible with the self aligned silicide technology described above.